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Guides
- RTL and hardware version-control documentation
Task-focused guides to installation, hardware-aware version control, RTL navigation, AI review, verification and project operations.
- Use the AI assistant
Configure access, limit shared context and approve candidate work explicitly.
- Activate and manage access
Complete secure activation and distinguish allowances, devices and external costs.
- Changes and version control
Choose the right Git layer or retained hardware comparison before reviewing a change.
- Manage sources and dependencies
Keep native source authority and import reviewed dependencies reproducibly.
- Telemetry and packet walkthroughs
Inspect two real digital-IP examples and their independent application contracts.
- Your first RTL project
Open native sources, inspect the design and review one bounded change.
- Hardware engineering glossary
Distinguish architecture, RTL, netlists, evidence and approval concepts.
- Install SiliconForge
Verify and install Windows x64 or Linux AMD64/ARM64, then open a local project.
- Update, back up and uninstall
Preserve project history and validate replacement runtimes safely.
- Navigate architecture and RTL
Trace hierarchy, connections and source without confusing abstraction levels.
- Package and export a project
Check readiness, export committed trees and verify offline packages.
- Configure project inputs
Understand discovered tops, EDAM build profiles, parameters and include paths.
- Diagnose and recover
Preserve projects, isolate failures and prepare a minimal safe support report.
- Configuration and automation reference
Discover typed RPC capabilities and diagnostic/source-checkout commands.
- Keyboard and canvas controls
Navigate scopes and selections with view-aware keyboard controls.
- Simulate and inspect waveforms
Check testbench intent and examine bounded VCD/FST signal windows.
- Synthesis and formal checks
Read netlist evidence, assumptions and solver results without overclaiming.
- Configure engineering tools
Understand tool authority, platform support and why a missing check is not a pass.
- Read verification evidence
Run checks and interpret revision-bound diagnostics and artifacts.
- Review and apply candidates
Prepare frozen file candidates and distinguish notes, approval, apply and reject.
- Save and compare checkpoints
Keep local engineering snapshots distinct from Git commits and backups.
- Work with external Git tools
Coordinate local native review with branches, remotes, backups and team Git workflows.
- Stage and commit local changes
Initialize local Git history and review whole-file staging before committing.
- Review hardware differences
Inspect architecture, RTL, source and uncertain matching in a bound comparison.
- Browse history and merge parents
Inspect local refs and immutable commit comparisons without switching branches.
- Recover from stale or conflicted state
Preserve work and recover safely from changed HEAD, index, locks and conflicts.
Product
- AI-assisted RTL design and verification
SiliconForge is a native Windows and Linux application for Verilog and SystemVerilog design, AI-assisted changes, hardware review and verification evidence.
- Platform and tool compatibility
Supported Windows and Linux architectures, engineering tools and documented limitations.
- RTL design and review demo
See the native SiliconForge workspace, a clearly labeled product overview, and a real read-only Codex RTL review. Captions, transcripts, and evidence boundaries included.
- Native RTL revision walkthrough
Explore a genuine native revision review with seekable chapters, a transcript and a step-through tour.
- Download SiliconForge
Windows x64 and Linux AMD64/ARM64 releases, system requirements, signatures and verified installation instructions.
- Pricing and subscriptions for RTL engineering
Compare SiliconForge Solo and Team subscriptions for native RTL engineering, including AI allowances, limits and availability.
- Verilog and SystemVerilog design workspace
Explore Verilog and SystemVerilog, review hardware changes and inspect revision-bound verification evidence in the SiliconForge native application.
- SiliconForge releases
Release history, published platforms and links to version-specific changes.
- SiliconForge 0.1.0 release notes
Platform availability and known limitations for SiliconForge 0.1.0.
- SiliconForge 0.1.1 release notes
GUI-first setup, numbered releases and recovery improvements in SiliconForge 0.1.1.
- SiliconForge 0.1.2 release notes
A consistent SiliconForge identity across the website, application and installers.
- Set up your first SiliconForge project
Choose Windows or Linux, verify your download and follow a reproducible first RTL project.
- RTL design, review and verification workflows
Follow a digital-IP workflow from requirements and an approved AI plan to an isolated RTL candidate, verification evidence and human review.
Examples
- Digital RTL and IP design examples
Run a self-contained SystemVerilog stream-register example with source, testbench and expected results, then explore native RTL review and waveform walkthroughs.
Support
- Data handling and AI routes
See what stays local, what managed and personal AI routes send, and how billing, support and runtime records are stored.
- Frequently asked questions
Answers about SiliconForge scope, platforms, Git interoperability, AI access and engineering evidence.
- Update and rollback
Recover safely from a SiliconForge application update.
- Security
How SiliconForge handles project boundaries, AI execution and software distribution.
- Support
Get help with installation, project workflows, activation and billing.
Company
- About SiliconForge
SiliconForge is a native digital RTL/IP engineering workspace provided by Denis Miclea in Canada. Find product scope and contact routes.
Legal
- Commercial software license
Read SiliconForge’s commercial software license and the separate rights for bundled third-party components.
- Privacy
Understand data handling for the SiliconForge website and application.
- Refunds and cancellation
Subscription cancellation and refund policy.
- Terms
Commercial terms for SiliconForge.
- Third-party notices and source
Find SiliconForge application license texts, component inventories, SBOM and pinned third-party source information.