Hardware engineering glossary

Applies to SiliconForge 0.1.2 · Updated 2026-09-30. Check platform limits.

Before this task: See the terms in a runnable example →

Use precise terms when discussing a design or reviewing a result. Many apparent contradictions come from comparing different representations, scopes or evidence.

Design and project terms#

RTL

Register-transfer-level source describing digital behavior and structure. It is not a PCB layout, analog schematic or completed physical chip.

Module definition / instance

A module defines reusable logic; an instance is one occurrence in a design. Multiple instances can share a definition and still have different parameters, connections or context.

Top module

The elaboration or simulation entry point. A testbench top and the synthesizable DUT top are often different.

Elaboration

Resolving modules, parameters, generates and connections for a particular configuration. Parseable source is not necessarily a successfully elaborated design.

Architecture / RTL hierarchy / connections

Major responsibilities and aggregated communication; instance containment; and exact wiring, respectively. They answer different navigation questions.

Native source / derived artifact

The editable source authority versus a graph, copied build input, waveform, report or transformed netlist. Editing a build copy need not change the native design.

EDAM / build profile

A project build description emitted by tools such as FuseSoC/Edalize, and SiliconForge's supported hash-bound interpretation of its inputs. Not every EDAM shape is supported.

Dependency / block

An upstream project with source/lock/license provenance versus an instantiated RTL object. Linking a dependency does not wire a block into your design.

Protocol and measurement terms#

Ready/valid transfer

A transfer occurs on the relevant clock edge when both ready and valid are asserted, according to the interface contract.

Backpressure

A receiver delaying acceptance. Check whether valid/data must remain stable and how buffering affects upstream readiness.

Latency / throughput

Delay from an accepted input to the specified output event versus work completed per unit time. Queued/stalled latency is not unloaded latency.

Synchronous reset

Reset sampled at a clock edge. Polarity, priority and state-clearing rules still depend on the design contract.

Saturation

Clamping an arithmetic result to a range boundary rather than wrapping it. Signed width and offset rules matter.

CRC

A specified cyclic redundancy check; polynomial, initial value, reflection, final XOR and wire byte order all matter. “Uses CRC-32” alone may be ambiguous.

Verification terms#

Lint

Static diagnostics; not proof of intended behavior.

Simulation / waveform

Execution under chosen stimulus and the resulting time-indexed signal values. Untested sequences remain unknown.

Assertion / assumption / cover

A required property, a constraint on the formal environment, and a reachability question. Incorrect assumptions can make assertions vacuous.

Bounded check / unbounded proof

Reasoning within a finite exploration bound versus a proof not limited to that bound under its method and assumptions. Do not interchange the labels.

Synthesis / netlist

Transformation of supported RTL into cells and nets. Generic synthesis resources are not physical area, target LUTs, timing closure or measured power.

Equivalence

A relation between two designs under stated interfaces and assumptions. It does not establish that either meets an unstated requirement.

Application contract / assurance

Explicit useful behavior and constraints, and checks evaluating a compatible candidate against them. A generic green check is not a replacement.

Source binding / stale evidence

Identification of exact inputs used by a run, and evidence whose inputs no longer match the thing being reviewed.

Qualification / evaluation

Checking that the harness can distinguish correct and faulty behavior, versus applying it to a particular candidate.

Review and delivery terms#

Candidate / applied change

A proposed isolated revision versus a change explicitly accepted into the working project. A completed AI response is neither automatic approval nor application.

Checkpoint / Git commit

A SiliconForge revision-state concept versus a Git history object. See the version-control documentation for exact supported operations.

Checksum / signature

Byte-integrity comparison versus a provenance statement under a signing trust policy. Neither proves engineering correctness or absence of every vulnerability.

Project package / application installer

A digital-IP handoff versus the SiliconForge software distribution. Their readiness, formats and authorization boundaries differ.

Managed unit / model token

A product usage allowance versus a model text-processing unit. One is not a universal fixed conversion into the other.

Apply the terms in the first project, project configuration, verification review and packaging. When a result is ambiguous, preserve the original label and inspect its source/configuration binding rather than upgrading the claim.

Need help? Report an issue. Include your application version; never include credentials.