SiliconForgeInstall SiliconForge
Choose your platform, verify the download and configure your tools.
Installation guide →SiliconForge · Windows & Linux
Design and verify your RTL.
A native workspace for Verilog and SystemVerilog. Explore your design, review AI-proposed changes, and run your engineering tools in one place.
Linux AMD64 · Linux ARM64 · Windows x64 · First time here?
01 / Explore your RTLActual application
Understand the designNavigate modules, ports and source.
Approve the changeReview the plan before execution.
Inspect the resultsTrace checks back to their inputs.
02 / Review the change
Review the change. Trace the logic.
Compare source revisions alongside the RTL they describe. Trace a changed signal to its driving logic without losing the project context.
This packet-filter capture shows a source relationship, not behavioral equivalence or a passing verification result.
Explore hardware-aware review →Changed ready-signal pathNative RTL view
03 / Inspect the evidence
From simulation output to individual signals.
Run your configured HDL tools and inspect logs, source and waveforms. Keep the result attached to the design and inputs that produced it.
How RTL verification works →Stream-register example / Icarus waveformActual application
A controlled AI workflow
Your approval comes before execution.
Ask about the design, review the proposed scope, then decide what runs. Inspect the candidate before applying it to your project.
- 01
Ask
Start with a question about your RTL and the context you choose to share.
- 02
Plan & approve
Review the proposed files, work and checks before execution.
- 03
Execute & check
Inspect the isolated candidate and results from configured tools.
- 04
Review & apply
Accept or reject the change. Resolve stale project state before applying.
Recorded in the native application
Watch a real RTL change.
Ask, plan, approve, execute and review. See the source and engineering checks—not a simulated product interface.
Watch the complete demonstration →Try it with a real design
Start with a working example.
Start with the self-contained stream-register example: source, testbench and expected results. Then deliberately break it to see how a failing check is reported.
Open your first project
Load the design through the GUI and run its assertion-based simulation.
First-project guide →Review a hardware change
The separate packet-filter tour shows revision history and source-derived RTL. Its complete source bundle is not included.
Examples and walkthroughs →Digital RTL/IP engineering—not analog, PCB design or physical chip sign-off. External HDL tools are separate dependencies. Platform and tool compatibility →
SiliconForge for Windows and Linux
Open your next RTL project.
Download the native application or review the plans and AI options first.