Compatibility / Know your environment
Check your platform and toolchain.
Application availability, AI execution and HDL-tool support are separate questions. Use this checklist before adopting SiliconForge for an existing RTL project.
Published application channels: Linux AMD64 · Linux ARM64 · Windows x64. Check exact artifacts and signatures →
Application targets
| Target | What to check | Important boundary |
|---|---|---|
| Linux AMD64 | uname -m reports x86_64; graphical session works; archive matches the channel | Distribution libraries and individual HDL tools still need diagnostics |
| Linux ARM64 | uname -m reports aarch64 or arm64; use the ARM64 archive | An ARM64 application is not proof of an ARM64 build of every external tool |
| Windows x64 | x64 operating system; valid installer signature; supported isolated WSL setup for AI execution | Native application, native tool checks and WSL AI isolation are distinct evidence surfaces |
macOS, Windows ARM and 32-bit targets are not public application channels. The website does not claim a universal minimum RAM, project-size limit or support for every Linux distribution: resource demand depends on the project and external checks.
Windows release signing and scanning do not stand in for interactive GUI qualification. See the release-specific evidence limitations.
Project inputs and portability
- Digital RTL: Verilog/SystemVerilog source with an explicit top module, source-file list, include directories, defines and parameters.
- Git workflows: install Git and check the repository root before staging or committing. Native design review complements documented Git operations; it is not a claim of every Git-client feature.
- Elaboration: supported constructs depend on the parser/elaborator and configured inputs. An unresolved module or missing include must be fixed before treating the graph as complete.
- Case and paths: check filename case, relative includes and tool paths when moving between Windows and Linux. A project that resolves on one machine may need environment changes on another.
- IP and dependencies: supply only source and dependencies you are authorized to use. Catalog IP and vendor tools are not included by implication.
Bundled and additional engineering tools.
| Tool family | Role | Verify before relying on it |
|---|---|---|
| Slang | SystemVerilog parsing and elaboration | Resolved executable, source set, top and language support |
| Verilator / Icarus | Supported lint and simulation flows | Testbench compatibility, compiler/runtime dependencies and trace format |
| Yosys | Synthesis and supported formal preparation | Frontend, target, synthesis script and interpretation of statistics |
| SymbiYosys / solver / EQY | Configured property and equivalence flows | Supported engine, assumptions, depth, configuration and applicable result scope |
| cocotb | Python-driven simulation tests | Python/simulator compatibility and independent stimulus/oracle quality |
Published application packages include engineering tools, while the Engineering Tool Pack is not offered as a separate download. Inspect the installed platform inventory before adding tools, and use the matching package’s source and notices. Follow the documented external-tool route; do not bypass integrity or authority checks by pointing at an arbitrary binary. Each tool retains its own licensing and source obligations.
Local work and network access
The application has a local core and local project/evidence storage. Managed AI, hosted checkout, activation and external providers require their applicable network services. Do not interpret local operation as an unlimited offline commercial entitlement or offline access to a remote model.
For Windows AI, use the supported isolated WSL route. A working WSL command does not prove a native Windows executable works; do not relax isolation or expose additional drives to get around a setup failure.
AI routes and setup → · Data disclosure → · Activation and usage →
Test your project and tool configuration
- Install and verify the correct application artifact.
- Open a small representative project and resolve elaboration diagnostics.
- Run the first-project reset/stall check, then the exact external check you need. Inspect commands, outputs and artifacts.
- Record any unsupported operation before moving to a larger design.
If a step fails, record OS, CPU, release, tool versions and the visible error. Keep secrets and private source out of the report unless an appropriate disclosure has been agreed.
Get setup help →