Navigate architecture and RTL

Applies to SiliconForge 0.1.2 · Updated 2026-09-30. Check platform limits.

Before this task: Resolve the intended design first →

Choose the representation that answers your question before zooming into detail. A block diagram, elaborated hierarchy and synthesized netlist describe different things.

Start with a current index#

Open the project, confirm its native source root and resolve indexing/configuration errors. A diagram built from missing files, stale copied sources or a different top can be misleading. Use project input inspection when the displayed design differs from your expected build.

Architecture, hierarchy and connectivity#

Architecture

Major modules and aggregated interfaces in system context. Use this for responsibilities and communication, not individual synthesized cells.

RTL Hierarchy

Elaborated instance containment. A child instance is not a later stage in a pipeline; two instances of the same module have different identities.

Connections

Exact module ports and wiring in the current scope. Follow endpoints; crossing lines do not automatically form a junction.

Netlist

Optimized cells and nets from a current synthesis artifact. Source-level objects need not survive synthesis unchanged.

Device

A separate representation requiring corresponding implementation evidence. A visible label is not proof of available placement/routing or a board-ready design.

Trace a signal and return#

1. Open Design → Architecture and search for the relevant block or responsibility. Select it and inspect its instance/source information.
2. Enter the block scope when you need its children. Distinguish entering from expanding a block in place: they change the visible context differently.
3. Switch to RTL Hierarchy and Connections for exact instance and port relationships. Follow a port to its connected endpoint and open the linked native source.
4. Check bit width, direction, reset and any handshake condition in source. For a telemetry FIFO, identify both the sample-accept and sample-deliver conditions; a connection line alone does not describe either.
5. Use breadcrumbs, back or up navigation to return. Frame a selection for readable detail instead of fitting an entire large design into one screen.

Expected result: you can identify the source-backed instance and explain the connection at the appropriate abstraction level without confusing a module definition with one of its instances.

Native source and derived views#

Source navigation should take you to the native file and relevant location, not an unrelated generated build copy. Compare the file path with the active project. A synthesized cell may have partial or transformed source mapping; do not invent an exact RTL relationship where the tool did not preserve one. Canvas selection is useful assistant context, so check the included selection before sending a request.

Keyboard and focus#

Click the canvas before using canvas commands. F frames the design, Shift+F frames a selection, and Home restores readable framing where supported. Alt+Left goes back and Alt+Up goes up a scope. The active view's action menu and configured bindings are authoritative; see the shortcut reference. Text fields keep their normal editing behavior.

Create and edit project files in the GUI#

Connect the intended project and activate paid access before creating a file. In the application menu choose New project file…; you do not need a terminal or an AI request.

1. Enter a project-relative path such as rtl/helper.sv, clock.sdc, README.md or LICENSE. Existing files are never overwritten.
2. Enter the content you intend to save, review it, then select Create project file.
3. The created file opens for editing and is available in Project → Files. Use Ctrl+S to save later edits; unsaved drafts are not verification inputs.

Alongside supported HDL files, this dialog accepts timing-constraint text (.sdc/.xdc), documentation (.md/.rst), and README, LICENSE, COPYING or NOTICE names, optionally ending in .txt. Files must be bounded UTF-8 text, no larger than 1 MiB, inside the project. Choose license text you are entitled to use; creating a file does not grant third-party rights.

Writing a constraints file does not apply its contents. Documentation and constraints are not automatically HDL compilation inputs. Inspect the project configuration and configured checks before relying on a timing or verification result.

If creation could not be confirmed after a connection failure, keep the draft and inspect Files in the original project before trying again. For a failed open, the previous document and its unsaved content remain separate from the requested file; do not assume the displayed body belongs to a file that failed to load.

When an object appears missing#

Check the active project, current scope, representation, filters, collapsed blocks and indexing diagnostics before concluding RTL was deleted. If labels are too small, use readable framing or focus a selection rather than repeated fit-to-view. If source links or graphs look stale after an edit, resolve the source/profile mismatch and refresh indexing; preserve the failing project state for a minimal reproduction.

Related: first project, synthesis artifacts, worked designs, diagnostics.

Keep your drafts when closing#

If source documents have unsaved edits, closing offers Save, Discard and Cancel. Save uses the same original-file hash check as the Source editor for each edited file. A conflict, permission error, disconnected core or unconfirmed save keeps the application open and preserves remaining drafts. Files already saved before a later failure stay saved. Discard closes without writing unsaved edits; Cancel leaves the workspace open. Project switching remains blocked while unsaved drafts belong to the current project.

Need help? Report an issue. Include your application version; never include credentials.