Watch an AI-assisted RTL change

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The workflow, in plain text.

A ready/valid stream register gains a WIDTH parameter, with an 8-bit default and a 16-bit testbench instance. The original project stays unchanged until the final native Apply action.

1. 00:00 · Context and capture disclosures
2. 00:04 · Know what AI can see.
3. 00:14 · A scoped change. A visible plan.
4. 00:24 · Execution starts with your approval.
5. 00:31 · Work in a candidate.
6. 00:36 · Ready for your review.
7. 00:44 · Read the proposed source changes.
8. 00:53 · Review first. Validate the exact candidate.
9. 01:15 · The checks pass. Apply stays explicit.
10. 01:22 · One last look before Apply.
11. 01:33 · Your project changes only when you decide.
12. 01:46 · Explore the workflow

The recorded candidate passed lint, compilation, simulation and synthesis. Human review is still necessary: the small test does not prove all widths or every possible input. The support question also demonstrates the assistant checking available tools and giving the support-form fallback without pretending the mailbox has been verified.

Download the timestamped transcript · Try the first-project guide

At your pace / Guided recorded example

Separate examples of the native views.

These older packet-filter and waveform examples are separate from the parameter-width change in the main recording. Original uncut history recording · Earlier edited history tour · Earlier tour captions. In that earlier tour, a 13.5-second wait is omitted and a readable source diff is not shown in this recording. No engineering result is changed.

These are genuine stills from the native capture session, not a runnable browser application. Step through them to understand what each view can—and cannot—tell you.

1. Orient in the architecture

Start with the retained packet-filter example. Modules and connections help you find the logic you want to inspect; a diagram alone does not establish correct behavior.

2. Read the selected source revision

Changes → History keeps the actual local commit and its source difference together. Inspect the ready-condition change in frame_storage.sv; selecting a history entry does not change HEAD.

3. Follow a partial RTL cone

Inspect the source-derived synthesized view around the selected ready signal. Its revision label and scope controls matter: this is a partial cone, not the entire design or functional-equivalence proof.

5. Try a separate simulation example

The stream-register exercise runs a small assertion-based testbench and opens its waveform. This is a different project; it does not verify the packet revision above.